m_�R�� �����Ew�q���z-?�9�G�i-eXT�vV2/��Ÿ�uy\Q�����y����\��uUI֥,��*����0y��g�!��x�RD� b���˙��+ːͩŁ��~Y�I�ʝb5��L/yY��_����Q�����\2(>��.�^�RS����, ���8wu!���v�xx[O��c羱�x� b�I��C�m�M����aR,bD�BB����0� QQ��0*Vom��� RP���h� ‘DIV (2)’ – The 200 MHz clock at the output of clock mux is coming from the clock divider ‘DIV (2)’, thus ‘DIV (2)’ should function as a divider throughout the scan mode, so that we will get the required 200 MHz clock.

The divider ‘DIV (2)’ always divides the input clock by a constant value of 2; typically in such dividers the functional control, excluding the reset to divider is likely to be tied to a constant value in the design.

There is also a clock mux, which has a functional control that selects which clock it should propagate at its output. If we scan the divider, the logic responsible for dividing the clock will become part of scan chain and will toggle during scan mode, resulting in clock of unpredictable frequency at the output of divider; so we should not scan this divider. 0000002701 00000 n Careful design of the clock generation and distribution circuits is now required for all high performance processor designs. double edge clocking, can be explored to incorporate into the new flip-flop to build clocking systems. 0000001325 00000 n trailer << /Size 96 /Info 78 0 R /Root 81 0 R /Prev 129884 /ID[] >> startxref 0 %%EOF 81 0 obj << /Type /Catalog /Pages 76 0 R /Metadata 79 0 R /PageLabels 74 0 R >> endobj 94 0 obj << /S 292 /L 357 /Filter /FlateDecode /Length 95 0 R >> stream

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In stuck-at testing the frequency of the clock domain we will be testing doesn’t matter; but in at-speed testing, we should be testing the clock domain at the maximum frequency it supports because of the reason discussed here. 9/27/18 Page 4 The frequency shown in red inside the clock domains (cloud like structures) in Figure 4, indicates the maximum clock frequency of that clock domain. Since we are bypassing the divider, we can scan this divider as it will not affect the divider output.

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This model is used for adequately representing longer interconnect wires.

‘DIV (1 or 4)’ – We need the undivided clock of 500 MHz (fastest clock), thus we need to mask the functional control to select the undivided clock in scan mode, as shown in Figure 3. The clocking architecture of a design needs to be modified to support ‘Scan’ operation. 2. 0000005291 00000 n 0000001171 00000 n As discussed here, the OCC controls the clock operation required for testing a circuit.

Now let us go through the modifications needed in clocking architecture for making the design ‘Scan’ friendly –. As shown in Figure 1, there is a PLL which is generating three different clocks (of frequency 500 MHz, 400 MHz and 100 MHz). 0000004004 00000 n Clock mux – Maximum possible frequency at the output is 200 MHz. X������ D@��X.

Figure 2: Distributed RC Advantage Provides accurate model of behaviour of wire used in the circuit. 0000002093 00000 n

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